Receiver Digital Linearisation

The receiver forms a key component in many military and commercial systems and can represent a significant proportion of the design effort and cost, as well as being a significant factor in the overall system performance.

Digital linearisation offers the potential to increase performance, reduce costs and/or reduce the size of the receiver. The ATC (Great Baddow) has been developing digital linearisation algorithms for both analogue receivers and electro-optical high speed sampling receivers.

Receiver Performance

Some of the main measures of the performance of a receiver are the final sampled signal bandwidth, the spurious free dynamic range (i.e. the linearity) and the noise figure. Often it is the Analogue to Digital Converter (ADC) that is the limiting factor of the system but gradual improvements in ADC design have meant that in some applications the analogue components in the system are now the main limitation. In analogue receivers to achieve high linearity the mixers have to be driven at high powers and manufactured to high specification and may require manual tuning every individual receiver. This significantly increases the costs. In the cases where the ADC has greater linearity than the mixer this potentially allows for the overall linearity to be increased, after sampling, in the software. It also opens up the possibility of reducing the power requirements and using alternative more compact receiver designs which would previously not have been considered as otherwise they would not meet the linearity or noise requirements.

Digital Linearistion Method

The basic approach requires the injection of calibration signals for sampling by the receiver. The linearisation algorithm determines the transfer characteristics of the receiver from measurements of these signals and an inverse is derived. The inverse is then applied to the normal input signal without the calibration signals present. Depending on the application, the calibration may only need to be performed once at the time of manufacture or may be sensitive to drift or temperature variation and would have to have to be calibrated more frequently, including being incorporated into the hardware architecture as part of the Built In Test Equipment (BITE). It is the development of the linearisation algorithms that has been the focus of the work at the ATC. This work is still at a relatively early stage but has been demonstrated successfully on a test receiver and shows potential for being a key aspect of future receiver design.

Example application: Radar Receivers

Very high linearity and small size are two drivers in radar receiver design. Even for a radar with only a few processing channels the receiver development represents a significant design challenge. For a phased array with a large number of subarrays the practical problems escalate, although the cost is still dominated by the transmit-receive (TR) modules. In order to take this further to building an Element Digitised Array a receiver would be required at every element. One of the objectives of the digital linearisation is to address future challenges such as Element Digitised Arrays but which also feedback benefits to other more current applications.

Example: Electro-Optical Samplers

The ATC has built an electro-optical sampling receiver demonstrator capable of sampling at multi-GHz rates and operating up to high frequencies. The linearity performance of the receiver is a trade-off against noise performance in a similar way to analogue receivers and so digital linearisation offers similar potential benefits. The same general approach has been taken to that used for the analogue receiver case, although the differences in the architecture and the sources of linearity necessitate some differences in the algorithm. Work to date has demonstrated that the linearisation can usefully improve the linearity of the sampler.